1. Field of the Invention
The present invention relates to the field of electronic packaging, particularly a method and resulting structure for a high speed chip carrier.
2. Description of Related Art
High speed computers typically require minimal inductance between the signal lines that link the integrated circuits (ICs) of the system. The ICs are usually mounted into chip carriers which have a plurality of leads that interconnect the chips and the signal lines. The leads are typically parallel, which creates an unacceptable amount of inductance between the leads, particularly between the power and signal lines. This problem becomes greater as the speed of the system increases.
U.S. Pat. Nos. 4,891,687 and 4,835,120 issued to Mallik et al, discloses an IC package that has a pair of copper plates bonded to the lead frame of the package. The copper planes are separated by insulative material and have tabs that are connected to designated leads of the lead frame. The power and ground pins of the IC are attached to each conductive plate respectively. Power flows into the package, from the leads, through the plates and into the IC. The creation of separate power and ground planes eliminates the parallelism between the leads, which reduces the inductance and increases the capacitance of the signal lines. This reduction in impedance is particularly important for high speed circuitry.
Although the dual plane package reduces the noise within the lines, the specific inductance and capacitance values are somewhat unpredictable because of the size and tolerances associated with the plates. Furthermore, there is no way of connecting passive components to the lead frame to customize the package. It would therefore be desirable to have an IC package that would allow the designer to control the impedance and noise of the circuit within the package. It would also be desirable to have a method of constructing an IC package that can provide internal routing with the package.